Foretellix

Ziv is a verification visionary and a passionate leader. Until recently Ziv served as Corporate VP at Cadence running the simulation and verification business. Through his career at Cadence, Verisity and Intel, Ziv led the development of verification businesses including chip simulation and Verification IP, industry first Coverage Driven Verification solutions and test bench products including Specman for chip verification and Perspec for SoC HW/SW verification.

Yoav is a world expert and leader in VLSI verification. He Invented the “e” verification language (later followed by the UVM methodology) and related methodology for verifying integrated circuit designs. Yoav founded Verisity (acquired by Cadence Design Systems for $315M in 2005) to deliver "e" verification process automation (VPA) tools. Verisity was In the last few years, Yoav has been researching complex-system verification.

Gil is a former Vice President of Intel Corp. Gil has 30 years of experience working for Intel , in which he led the development of EDA and CAD tools in all design domains as well as leading VLSI design projects. In his recent years he was in charge of (among others) the verification tools development organization within Intel.

Carl Peter Forster, Advisory Board Member – Mr. Forster has over three decades of senior operational automotive industry experience with companies such as BMW, Opel AG, General Motors Europe, and Tata Motors. Since 2013, Forster has been a board member at Geely Automobile, Volvo Cars, Gordon Murray Design, and Hella.